The recent advances in very deep sub-micron (VDSM) integrated circuits (ICs) have brought new challenges in the physical design methodology process of integrated systems.
For example, most conventional electronic circuit design tools focus on post-layout verification to verify, for example, whether parasitics satisfy the corresponding constraints when the entire chip design is complete and detailed information about the parasitics of the physical designs and the currents drawn by the transistors are known. In these conventional approaches, the parasitics are extracted from the completed layout and then verified against the corresponding constraints. Moreover, the conventional circuit synthesis step is followed by layout synthesis, and each step is carried out independent of the other in these conventional approaches. This is again followed by a physical or formal verification step upon the completion of the entire physical layout to check whether the desired goals have been achieved after layout generation and extraction. These steps are carried out iteratively in the conventional approaches till the desired performance goals are met.
Nonetheless, such an iterative approach wastes significant amount of resources because various physical design tools, such as the placement tool, the router, etc., and various schematic design tools, such as the schematic editor, the schematic level simulator(s), etc., are unaware of the parasitics associated with the physical design of the electronic circuit and the electrical characteristics associated with the parasitics.
Thus, there exists a need for constraint verification for implementing electronic circuit designs with electrical awareness early in the design stage.